Simple alu | Computer Science homework help

Prompt

In this project, you will design and build a simple CPU on Logisim and write programs that can run on it. If you haven’t yet, you can download Logisim by following this link: http://www.cburch.com/logisim/download.html

Your design will go through four phases. In the first phase, you will design and build the ALU using Logisim. In the second phase, you will design the instruction set that implements the instructions you designed in phase one. In the third phase, you will design and implement a control unit for this ALU using Logisim. By connecting the CU to the ALU, you will get a functional CPU. In phase four of the project, you will write assembly language programs for the CPU you built.

Phase One

Start by building an 8-bit ALU using Logisim. This ALU can implement 16 instructions on 8-bit operands. We would suggest the following minimum list of instructions:

· Arithmetic addition

· Increment

· Decrement

· Comparison (with 3 outputs: one for equals, one for less than and one for greater than)

· Logic bitwise Not

· Logic bitwise And

· Logic bitwise Or

· Register right logic shift

· Register left logic shift

In addition to these nine instructions, please suggest five more instructions that the ALU can implement for a total of 14 instructions (we are reserving 2 instructions for branching). Justify the importance of the five instructions you added in a Word doc to submitted as part of this assignment. Label these instructions as ‘Phase One.’

After you’ve suggested and justified your five suggested instructions, please build at least the nine above-mentioned operations as blocks in Logisim.

Phase Two

In phase two of the project, you are required to design the instruction set of the ALU/CPU as follows:

· Create the opcode table for the ALU by giving a binary code and a name for each instruction you built in Logisim in phase one.

· Decide how many operands you want your instructions to handle and justify your choice. We suggest either one operand with accumulator or two operands with the result stored in one of the input registers.

· In Logisim, add a multiplexer to the circuit you built in phase one that chooses one of the available operations. The simplest way to create this part of the CPU is to connect the outputs of the multiplexer to the inputs of AND arrays connected to the output of the operation blocks.

Please record your answer to phase two in the same Word doc and label it ‘Phase Two.’

Phase Three

In phase three, you are required to use Logisim to implement the control unit for at least the following three operations:

· addition

· logic bitwise AND

· right logic shift

In order to finish this phase, you need to add operand registers according to the decision you took for the number of operands in phase two and, if needed, a flag register.

Please record your answer to phase three in the same Word doc and label it ‘Phase Three.’

Phase Four

In order to be able to write assembly language for the CPU we need to add to instructions (without implementation):

· branch to an address (name it JMP)

· conditional branch to an address (name it CJMP and suppose that the jump takes place if the comparison operation result is ‘equals’)

Now, write the following programs using the assembly language you designed in the previous phases of the project as well as these two branching additional instructions:

· Write a program that adds two operands.

· Write a program that adds operands until the new value to be added is 0. You do not need to implement the input operations to modify the contents of the registers. Just assume that by the end of each iteration, the register content is modified.

· Write a program that increments by 2 the content of a register 10 times.

· Write a program that shifts the content of a register until the least significant bit is 0. Think of a way to stop shifting if the content of the register is 11111111 and add it to your program.

· Please record your programs in the same Word doc and label them under the section ‘Phase Four.’

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